1. Field of Invention
The present invention relates to a solid-state imaging device which is represented by a CMOS image sensor and a camera system.
2. Description of the Related Art
A CMOS image sensor may be manufactured using the same manufacturing process as a general CMOS integrated circuit, and may be driven by a single power supply. Also, an analog circuit or a logic circuit which uses a CMOS process may be mixed in the same chip.
Accordingly, the CMOS image sensor has great merit in that the number of peripheral ICs may be reduced.
In a CCD output circuit, one-channel (ch) output using an FD (Floating Diffusion) amplifier having an FD layer is the mainstream.
For this, the CMOS image sensor has an FD amplifier for each pixel, and the main stream of its output is a column parallel output type which selects any one row in the pixel array and simultaneously reads them in a column direction.
This is because since it is difficult to obtain sufficient driving capability in the FD amplifier arranged in the pixel, it is necessary to lower the data rate, and thus parallel processing is advantageous.
Several pixel signal read (output) circuits of column parallel output type CMOS image sensors have been actually proposed.
One of the most advanced types is a type which is provided with an analog-digital conversion device (hereinafter referred to as an “ADC” (Analog Digital Converter)) for each column and extracts a pixel signal as a digital signal.
The CMOS image sensor mounting such a column parallel type ADC thereon, for example, is disclosed in W. Yang et al., “An Integrated 800×600 CMOS Image System,” ISSCC Digest of Technical Papers, pp. 304-305 February, 1999) (non-patent document 1), or JP-A-2005-278135 (patent document 1).
FIG. 1 is a block diagram illustrating the configuration example of a solid-state imaging device (CMOS image sensor) mounting a column parallel ADC thereon.
As illustrated in FIG. 1, this solid-state imaging device 1 includes a pixel unit 2, a vertical scanning circuit 3, a horizontal transfer scanning circuit 4, and a column processing circuit group 5 composed of ADC groups.
Further, the solid-state imaging device 1 includes a digital-analog conversion device (hereinafter referred to as a “DAC” (Digital-Analog Converter)) 6, and an amplifier circuit (S/A) 7.
In the pixel unit 2, unit pixels 21, each of which includes a photodiode (a photoelectric conversion device) and an amplifier in the pixel, are arranged in the form of a matrix.
In the column processing circuit group 5, a plurality of column processing circuits 51, which form the ADC for each column, are arranged for the respective columns.
Each column processing circuit (ADC) 51 has a comparator 51-1 which compares a reference signal RAMP (Vslop) that is a ramp waveform (RAMP) obtained by changing a reference signal generated by the DAC 6 to a stepwise form with an analog signal that is obtained from a pixel through a vertical signal line for each row line.
Further, each column processing circuit 51 has a counter latch (memory) 51-2 that counts the comparison time of the comparator 51-1 and maintains the result of count.
The column processing circuit 51 has an n-bit digital signal conversion function, and is arranged for vertical signal lines (column lines) 8-1 to 8-n. Accordingly, a column parallel ADC block is constructed.
Each output of the memory 51-2 is connected, for example, to a horizontal transfer line 9 having a width of k bits.
Also, K amplifier circuits 7 that correspond to the horizontal transfer line are arranged.
FIG. 2 is a diagram illustrating a timing chart of the circuit of FIG. 1.
In each column processing circuit (ADC) 51, an analog signal (electric potential Vsl) read from the vertical signal line 8 is compared with a reference signal RAMP (Vslop) that is changed in a stepwise manner by the comparator 51-1 arranged for each column.
In this case, until the output of the comparator 51-1 is reversed through crossing of the analog electric potential Vsl and the level of the reference signal RAMP (Vslop), the counter latch 51-2 performs counting, and the electric potential (analog signal) Vsl of the vertical signal line 8 is converted into a digital signal (AD-converted).
This AD conversion is performed twice for each reading.
At the first time, the reset level (P phase) of the unit pixel 21 is read from the vertical signal line 8(-1 to -n), and the AD conversion thereof is executed.
At the reset level (P phase), the difference for each pixel is included.
At the second time, the photoelectrically converted signal for each unit pixel 21 is read from the vertical signal line 8 (-1 to -n) (D phase), and then the AD conversion thereof is executed.
Since the difference for each pixel is included even in the D phase, a correlation double sampling is realized by executing (D phase level—P phase level).
The signal converted into the digital signal is written in the counter latch 51-2, is sequentially read in the amplifier circuit 7 through the horizontal transfer line 9 by the horizontal (column) transfer scanning circuit 4, and then is finally output.
As described above, the column parallel output processing is performed.